III. ORCAD/PLD

OrCAD's PLD directory is for programmable logic devices. PLDs are blank chips that you can customize in the lab with logic device programmers. These are also known as ASICs (Application Specific Integrated Circuits).

OrCAD's PLD compiler creates detailed logic from your high-level descriptions. You can choose from the following high-level ways to describe your design.

Boolean equations
Indexed equations
Numerical maps
State machine procedures
Truth tables
State equations

I will cover 1, 5 & 6.

The executable PLD statements start with a single pipe character ( | ). Comments start with no pipes or a double pipe ( || ).

1. Boolean equation description

    Operators  (some of them)
      =    assignment
      '    complement or NOT
      &    AND
      #    OR
     ##    XOR
     ??    Tri-state enable
     //    Rising edge of the clock
     \\    Falling edge of the clock

Examples:

1. B AND C with a tri-state output.: | Y = A ?? B & C

Y = B & C if signal A is active
Y is high impedance if A is inactive
2. A XOR B: | Y = A ## B

2. TT Description

    Examples:

    If we want to implement this TT

          AB | f
          00 | 1
          01 | 1
          10 | 0
          11 | 0


    we would use this PLD truth table format:

         | Table: A, B -> f
         | {  00b -> 1b
         |    01b -> 1b
         |    10b -> 0b
         |    11b -> 0b }

    If we want to implement this TT

          AB | x y
          00 | 1 0
          01 | 1 1
          10 | 0 1
          11 | 0 0

    we would use this PLD truth table format

         | Table: A, B -> x, y
         | {  00b -> 10b
         |    01b -> 11b
         |    10b -> 01b
         |    11b -> 00b }

3. State Equations.

Example:

If we want to implement a D FF with input B AND C and clock CLK.: | QD = CLK // B & C

B & C is latched into FF QD on the rising edge of CLK This is a registered output because it has a clock input.
If we want D FF A to have input A(B'+C): | A = A & (B' # C)

A receives a new state based on the old state of A, B' & C This is a registered output because it has a present and next state. Not showing the clock will not always work.

General Structure of PLD Files

A PLD specification has several parts, some of which are optional

A. Narrative description. Describes the logic in words. (optional)
B. Device code. Describes the specific device to be used. (required)
C. Input/Output signals. Lists signals connected to pins and to internal nodes of the device. (required)
D. Title. Gives formal title to the device. (optional)
E. Activity statement. Defines which signals are active-high or low. (optional Default is high)
F. Register statement. Defines which outputs have registers attached. (optional)
G. The logic. Boolean equations, TT etc. (required)
H. Test commands. Commands for logic simulation. (optional)

(PLD files are text files that can be prepared in a text editor.) Minimal PLD file source code (only B, C & G). Combinational logic.

          |   PAL12H6  in: (A[1~6], B[1~3,5~6]), out: Y[1~6]
          ||
          |      Y1 = A1 & B1      || AND
          |      Y2 = A2 # B2      || OR
          |      Y3 = A3 ## B3     || XOR
          |      Y4 = A4'          || NOT
          |      Y5 = (A5 & B5)'   || NAND
          |      Y6 = (A6 # B6)'   || NOR

Minimal PLD file source code (only B, C & G). Registered logic.

         |   PAL16R4   in:(CLEAR, PRESET), out:(A, B), clock:CK
         ||
         |     A = (CLEAR & B) # PRESET'
         |     B = (CLEAR & A' & B) # (CLEAR & A & B') # PRESET'

The PALs DO NOT require a clock as part of the state equations. BUT, the GALs DO require a clock as part of the state equations.

         |   GAL16V8   in:(CLEAR, PRESET), io:(A, B), clock:CK
         ||
         |     A = CK // (CLEAR & B) # PRESET'
         |     B = CK // (CLEAR & A' & B) # (CLEAR & A & B') # PRESET'

    The following example includes test commands.

         |  GAL16V8  in:(CLEAR, PRESET), io:(A, B), clock:CK 
         ||
         |   A = CK // (CLEAR & A' & B) # (CLEAR & A & B') # PRESET'
         |   B = CK // (CLEAR & B') # PRESET'
         |   Vectors:
         |   Display (CK,CLEAR,PRESET,A,B)c,"  TT  ",(A,B)L," count ",(A,B)d
         |   Test CK=0,1;CLEAR=0;PRESET=1
         |   Test CK=8(0,1); CLEAR=1; PRESET=1
         |   End

Starting the PLD Compiler

At the DOS prompt type:

C:ORCAD/PLD> PLD file

file: the text file (file.pld) described in all examples
Testing the logic

Once the PLD logic has been defined we can check if it works as we expect with the VECTORS command. If we placed the test commands in the .PLD file we will not have to do this. At the DOS prompt type:

C:ORCAD/PLD> VECTORS file

You will see a hyphen (-) prompt. At this prompt you will want to indicate what signals to display and in which format the signals should be displayed. Text in quotes "" will be displayed as text.

        - Display (CK,CLEAR,PRESET,A,B)c,"  TT  ",(A,B)L," count ",(A,B)d

        this will display CK, CLEAR,PRESET,A & B in chart form (note the c)
        and A & B in logic form (T & F) (note the L) and also A & B in digital 
        form (0 & 1) (note the d).

Once you have declared which signals you want to display and in what form the prompt will return. At this time you can indicate the input signals to use.

        - Test CK=0,1;CLEAR=0;PRESET=1

        this will pulse the clock once with the clear & preset values set as 
        shown.  That is, the registers (FFs) will be cleared.

Now that all FFs have a state (not U) we can run the circuit. Type:

        - Test CK=8(0,1); CLEAR=1; PRESET=1

        this will pulse the clock 8 times with clear and preset disabled.  The 
        outputs will be displayed as the simulation runs.