Topics for System-on-Chip Design

Comprehensive Exam

Posted: September 2006

Semiconductor Processing

Photolithography
Self-Aligning Gate
Chemical/Mechanical Polishing

ASIC Cell Layout

Simple MOSFET Models
Inverter Performance Parameters
Input Capacitance Estimation
Output Resistance Estimation
Transmission Gates
Library Exchange File Graphics

Register Transfer Language Coding

VHDL and Verilog Behavioral Descriptions
RTL Processes
Case and If-then Latch Generation

Finite State Machine Design

Mealy and Moore Machines
RTL Descriptions
State Diagrams
State Tables
Machine Schematics

ASIC Physically Knowledgeable Synthesis

Contents of Netlist File
Timing Constraints
Setup and Hold Times
Clock Skew and Jitter
Timing Arcs and Slack
Verilog File Functional Simulation

ASIC Place and Route

Power Routing
Buffer Insertion
Clock Tree Insertion
Filler Cells

Signal Integrity

Crosstalk
IR Drop and Ground Bounce
Electromigration
Substrate Noise

ASIC Chip Finishing

Power and Pad Rings
Design Rule Checks
GDSII